The present invention relates to integrated circuit manufacture and, more particularly, to the formation of metal interconnect structures for integrated circuits. A major objective of the present invention is to improve trench-depth precision in a dual-damascene process often used for making copper interconnect structures.
Much of modem progress is associated with the increasing prevalence of computers, which has, in turn, been made possible by advances in integrated-circuit manufacturing technology. These advances have led to ever shrinking dimensions for circuit elements. This shrinking has made it possible to place more circuit elements on a single integrated circuit for greater functionality. In addition, the circuits are closer together so that communication among circuit elements can be faster.
A typical integrated circuit comprises a semiconductor substrate in which circuit elements are formed, a submetal structure that can include transistor gates and contacts, as well as local interconnects, a submetal dielectric, and a metal interconnect structure. The metal interconnect structure is typically formed by depositing metal (for conducting signals) and dielectric (for electrically separating conductors), and patterning the deposited materials photolithographically.
For many years, aluminum has been the metal of choice for interconnect structures since it is a good conductor, it is readily patterned, and it is process compatible with the other materials involved integrated-circuit manufacture. However, as features sizes fall to deep submicron levels, the resistance of aluminum becomes a salient factor in limiting device performance. (The resistance of a conductor is inversely proportional to its cross section, which drops with reductions in both width and thickness of a conductor. A high resistance causes high-frequency electrical energy associated with fast integrated circuits to be dissipated as heat.) To overcome this limitation, integrated circuits have turned to a lower-resistance metalxe2x80x94copper.
While it addresses the problem of resistance, the use of copper introduces additional problems. Copper is relatively hard to pattern; however, a damascene process has been developed to address this problem. Another problem is that copper ions have a deleterious affect if allowed to migrate into the semiconductor substrate. To address this problem, barrier metal, such as tantalum, is used to encapsulate copper conductors to prevent the migration.
The damascene process involves depositing a silicon dioxide layer, patterning that layer to form trenches, depositing a conforming layer of barrier metal, depositing copper to overfill the trenches, and polishing the copper until it is flush with the silicon dioxide. In accordance with a xe2x80x9cdual-damascenexe2x80x9d process, vias can be formed by masking the patterned silicon dioxide before the barrier metal is deposited and etching apertures through silicon dioxide below the trenches where the vias are to be formed. The barrier metal is then deposited so that it conforms to the via apertures as well as the trenches. The copper then fills the via apertures as well as the trenches so that a single deposition provides for both conductors and vias.
Trench depth is a critical parameter. Trench depth corresponds to the eventual conductor thickness. Excessive variation in metal thickness can cause unpredictable timing. In addition, if the trenches are too shallow via apertures from the trench down to the underlying metal can be too deep. In that case, the via apertures can have excessively high height-to-width aspect ratios; this can make it difficult for the barrier metal and copper depositions to conform properly to the underlying surfaces. As a result of poor conformity, electrical connections can be impaired. Finally, if the trenches are too deep, the underlying dielectric may be so thin that its integrity is compromised; the result can be a premature dielectric breakdown, adversely affecting device performance lifetime.
The formation of trenches in a damascene process is not the only case in which etch depth is critical. However, in many cases, the goal of an etch is to expose a material that is different from the material being etched. Where the etch is to expose a different material, there are several approaches available to control etch depth. One approach detects when the different material is exposed. Sometimes this can be done by optically monitoring the surface being etched. In the case of a plasma etch, the plasma composition changes as it begins to etch the underlying material. The etching can then be detected by monitoring the spectral characteristics of the plasma itself.
Another approach, which can be combined with detection, is to use a differential etchant technique. If the etching process etches the overlaying material much faster than the underlying material, then the etch depth is less time critical as long as the underlying material is exposed. The differential etchant approach is particular useful for chemical etching where there are a number of etchants available with very different interactions with different materials.
As feature sizes have decreased, the use of chemical etchants has been reduced in favor of plasma etches. If a plasma does not etch the underlying material much slower than the overlying material, depth control becomes problematic. One solution is to xe2x80x9ccoatxe2x80x9d the underlying material with an etch-resistant material, which then serves as an xe2x80x9cetch stopxe2x80x9d. For example, silicon nitride can be used as an etch stop when etching silicon dioxide over polysilicon since silicon nitride has the slowest plasma etch rate of the three.
However, the use of a silicon-nitride etch stop in the context of a dual-damascene process is not favored since the silicon nitride has a substantial higher (7.0 versus 4.0) dielectric constant than silicon dioxide. The presence of silicon nitride would thus increase capacitance. The resulting performance impairment would offset much of the advantage achieved in lowering resistance by using copper instead of aluminum.
Accordingly, the prevailing method of controlling trench depth relies on timed etches based on estimated etch rates. While timed etches can be precise for shallow etches, the trenches involved in the dual-damascene process have depths that correspond to the desired conductor thicknesses. At such depths, the precision of the timed etches is not optimal. What is needed is a method that allows for more precise trench depths and, thus, more reliable copper-based integrated circuits.
The present invention involves the use of a marker layer with a dielectric constant lower than that of silicon dioxide to indicate when an etch is to be stopped. While overlaying silicon dioxide is being etched by a plasma, the optical spectrum of the plasma is monitored for the presence of an ionic form of a constituent of the marker layer that is not silicon or oxygen or any gas used to form the bulk of the plasma. The presence of the constituent in the plasma spectrum indicates that the marker layer is being etched. The etching can be terminated as a function of the detection of this constituent.
The method of the invention involves forming a lower silicon dioxide layer over a lower patterned metal, e.g., copper, layer. The low-k dielectric marker layer is deposited on the lower silicon-dioxide layer. An upper silicon dioxide layer is deposited over the low-k marker layer. The resulting structure is masked using an upper metal layer pattern, for example by using photoresist according to conventional photolithograpy. A plasma etch is performed through the trench-pattern mask.
During the plasma etch, the optical spectrum of the plasma is monitored in such a way that etching of the marker layer can be detected. For example, the marker layer can consist of fluorinated silicon oxide (SiOF). In this case, a spectral frequency associated with fluorine ions (and not with silicon or oxygen ions) can be monitored. When the etch reaches the marker layer, the spectral component associated with fluorine ions is enhanced.
The invention provides for a variety of ways of using the detection to determine when to terminate the etch. The etch can be terminated when the spectral component is first detected. The etch can be terminated a predetermined time after the spectral component is first detected. The etch can be terminated after the spectral component disappears. In this last case, the marker material is completely removed according to the mask pattern to expose the lower silicon dioxide layer. However, the first two approaches can be used to leave a predetermined thickness of marker layer in place over the lower silicon dioxide layer. Other variations are described subsequently.
In a dual-damascene process, the resulting structure can be remasked with a via pattern. Via apertures can then be etched to expose underlying conductors. Barrier metal can be deposited conformauly over the trenches defined by the trench etch and the vias formed in the via etch. Copper is then deposited to fill the via apertures and overfill the trenches. The resulting structure is chemical-mechanically polished (CMP) until silicon dioxide outside the trenches is exposed so that the trench pattern is assumed by the copper. The resulting structure can be passivated. The process can be repeated for additional metal levels.
The resulting structure has marker material in regions that were masked during the first (trench) etch. Depending on whether the etch of the marker layer was etched partially or completely through, there may also be marker material beneath the conductors formed in the trenches (except where vias are formed). If the etch was partial, then the vias can be partially coextensive with the marker material. If the etch was completely through the marker material, then the vias may not be partially coextensive with the marker material. In either case, the conductors, at least the barrier material thereof, can be in contact with marker material.
A major advantage of the invention is that the parasitic capacitance of the complete circuit is not adversely affected by the presence of the marker material. Relative to a method employing silicon nitride as an etch stop layer, the method provides for reduced parasitic capacitance.; the reduction in capacitance, in turn, improves timing and reduces power consumption. Relative to a method relying on a timed etch for determined trench depth, the present invention provides more precise control over trench depth. This control over trench depth translates in to control over metal thickness, thus providing for more predictable timing. In addition, there is less danger of dielectric breakdown due to an intermetal dielectric that is too thin and less danger of electrical discontinuities due to high-aspect ratio via apertures. These and other features and advantages of the invention are apparent from the description below with reference to the following drawings.